1. Field
Example embodiments relate to a focus control apparatus for controlling a focus in an optical system of a microscope.
2. Description of the Related Art
In order to perform a surface inspection of a semiconductor device, an optical semiconductor inspecting apparatus includes a microscopic system having a high precision automatic focus control performance to optically form an image from a fine pattern (for example, see Patent document 1). FIG. 8 is a view illustrating a general optical semiconductor inspecting apparatus. A light illumination portion 101 emits a light toward an optical system 102 of a microscope. Then, the light from the light illumination portion 101 is incident onto the optical system 102. The optical system 102 irradiates an irradiation light, using a reflection plate and the like disposed therein, to a surface of a semiconductor wafer 105 that is disposed on an XYZ stage 104. An image capturing device 103 picks up the surface of the semiconductor wafer 105, by a reflection light from the irradiation light. In here, a focus position control portion 106 detects a focal point dislocation of the optical system 102 and move the XYZ stage 104 in a direction parallel with an optical axis, that is, Z direction, to control a focus position.
In this case, the focus position control portion 106 detects a deviation amount of the semiconductor wafer 105 from the focus position of the optical system 102 of the microscope using the reflection light from an object to be detected, that is, the surface of the semiconductor wafer 105.
The focus position control portion 106 feedbacks a focus error signal to a stage control mechanism 107 that performs a three dimensional adjustment for X axis, Y axis and Z axis of the XYZ stage 104. The focus error signal indicates the deviation amount from the focus position.
Thus, the stage control mechanism 107 performs a position control in Z axis of the XYZ stage 104, by the feedback focus error signal, to focus the optical system 102 of the microscope on the surface of the semiconductor wafer 105.
FIGS. 9(a) to 9(c) are views illustrating a surface shape of the semiconductor wafer 105 to be detected by the semiconductor inspecting apparatus. FIG. 9(a) is a view illustrating a surface of the semiconductor wafer 105 where chips are formed. FIG. 9(b) is a view illustrating the region (R) of the semiconductor wafer 105. FIG. 9(c) is a cross-sectional view taken along the line B-B′ in the region (R) in FIG. 9(b).
As illustrated in FIG. 9(a), the semiconductor wafer 105 has a plurality of the chips 105T that are periodically arranged therein. As illustrated in FIG. 9(b), in case that the chip 105T is, for example, a semiconductor memory device, the chip 105T include a cell region 105C where memory cells are formed and a peripheral region 105P for wiring and reading data for the memory cells. Since a height of the cell region 105C is different from a height of the peripheral region 105P, a focus error signal indicating a deviation amount from a focus position in the cell region 105C is different from a focus error signal in the peripheral region 105P.
FIG. 10 is a view illustrating a real cross section of the semiconductor wafer 105 taken along the line B-B′ in FIG. 9(b). In FIG. 10, a horizontal axis represents a position of the semiconductor wafer 105 and a vertical axis represents a thickness of the semiconductor wafer 105.
As illustrated in FIG. 10, in reality, the semiconductor wafer 105 has different thicknesses and a curved surface shape. Accordingly, the focus error signal includes a component of a height variance due to an angle (θ) of the surface curvature.
FIG. 11 is a waveform graph illustrating a focus error signal along the cross section of the semiconductor wafer 105 in FIG. 10. In FIG. 11, a horizontal axis represents a position of the semiconductor wafer 105 and a vertical axis represents a voltage level. In here, the focus error detected due to the surface variance of the semiconductor wafer 105 is represented by the dotted line. A wave obtained by performing a low pass filtering of the focus error represented by the dotted line is represented by the dashed dotted line, and a focus error signal generated by applying an offset to the wave obtained by a low pass filtering is represented by the solid line. The focus position control portion 106 moves the XYZ stage 104 in Z direction using the stage control mechanism 107 based on the focus error signal of the solid line, to control a focus position of the semiconductor wafer 105.
FIG. 12 is a waveform graph illustrating a focus error signal along the cross section of the semiconductor wafer 105 in FIG. 10. In FIG. 12, a horizontal axis represents a position of the semiconductor wafer 105 and a vertical axis represents a voltage level. In FIG. 12, the position control of the XYZ stage 104 is performed using the detected focus error signal without a special process such as the low pass filtering in FIG. 11. Even though any focus error signal of FIGS. 11 and 12 is used, a high precision focus control is performed to optically inspect a defect on the surface of the semiconductor wafer (W). In other words, when the XYZ stage 104 moves in two dimension XY plane, it is required to move the XYZ stage 104 in Z direction in order to correct a focal point deviation that occurs due to the thickness variance.